Software programs for use in simulating integrated circuit design and predicting the operational behavior of the circuit are well known to those skilled in the art.
FIG. 1 shows a well-known general architecture of a data processing system 100 that can be utilized to execute a program implementation of a digital integrated circuit simulator. The data processing system 100 includes a central processing unit (CPU) 102 and a system memory 104 that is connected to the CPU 102. The system memory 104 typically stores the operating system for the CPU 102 as well as data and various sets of program instructions for applications programs to be executed by the system 100. For example, the system memory 104 could store a software program, i.e. a sequence of machine readable program instructions, needed to implement a method for using state nodes for the efficient simulation of digital integrated circuits at the transistor level in accordance with the concepts of the present invention. Typically, the computer system 100 also includes a display 106 that is connected to the CPU 102 to allow images to be visually displayed to a user, a user input system 108, e.g., a keyboard or mouse, that allows the user to interact with the system 100, and a memory access system 110 that enables transfer of data both within the system 100 and between the system 100 and systems external to the system 100, e.g. a computer network to which the system 100 is connected. All of these components and the ways in which they interact are well known to persons skilled in the art.
Conventional device level digital integrated circuit simulators, such as the well-know public domain tool IRSIM, supported by the University of California—Berkeley, work on “flat” circuits, that is, circuits that have no module hierarchy. Thus, a hierarchical circuit must be flattened to transistor level before it will work on these conventional simulators. This approach has a major drawback. Most digital circuits, whether custom designed (e.g., memories) or standard cell based (e.g., ASICs), make extensive re-use of the same building blocks or lower level modules. For example, the major portion of a static random access memory (SRAM) circuit is made up of multiple repetitions of the same six-transistor core cell. A flattened netlist of the SRAM design does not reflect this fact. Simulations of identical circuit modules are repeated for each occurrence of the module in the circuit, resulting in a relatively time-consuming operation.